Glossary

Reported 8 GB and 10 GB

Terms you will meet on the Discord and on this wiki, in plain words. For the card itself see CMP 170HX; for which version you have see Which card do I have.

The card

8 GB card, 10 GB card

The two production versions of the CMP 170HX, named by their stock memory. People also call them by what they unlock to: a 64 GB card is an unlocked 8 GB card, a 40 GB card an unlocked 10 GB card. Source: @mlx4, 2026-10-25 See 8 GB card, 10 GB card, Variant comparison.

GPC, TPC, SM

The compute blocks of the GPU, from large to small. GA100 has 8 GPCs and 128 SMs; the CMP 170HX ships with 70 SMs enabled. Fuses mark each block as enabled, disabled (switched off but working) or defective. Blocks marked defective have proven truly defective; disabled ones can be enabled. Source: @djpandaman, 2026-10-17

FBP, FBPA

Frame buffer partitions: the memory controllers that sit in front of the HBM stacks. GA100 has 12 FBPs and 24 FBPAs serving 6 HBM sites. Source: repo github.com/lixiangwuxian/170hx-rir-tool by lixiangwuxian on GitHub, posted by @lxtend, 2026-10-10 The 8 GB card uses 16 FBPAs, the 10 GB card 20. Source: repo github.com/matstatman/gpcprobe by matstatman on GitHub, posted by @matstatman, 2026-10-20 "Sixth stack" means the sixth HBM site, which decides whether a 10 GB card can reach 48 GB.

NDIV

The divider that sets the HBM clock (clock = NDIV x 27 MHz; NDIV 54 = 1,458 MHz, NDIV 64 = 1,728 MHz). Source: repo github.com/PixelML/club-170hx by PixelML on GitHub, posted by @c133, 2026-10-20 It is changed with 170tune. Whether it can change while the driver runs is Contested, in the order posted:

The idle p-state patches switch between an idle NDIV of 30 and a busy NDIV of 64 while running. Source: @robbbbbb7973, 2026-10-10
One owner found NDIV cannot be changed at runtime and must be set at boot. Source: @markshowa, 2026-10-26

HBM clock win

The speed gained by raising NDIV above stock. It only shows when the workload is memory-bound: NDIV 54 to 70 gave +10.5% at one user on dense Qwen3.8-27B, Source: @wakeupmbrc1, 2026-10-14 raising two NDIV 54 cards to 64 gave +5.8-6.3% single-user decode on GLM-5.3-Flash TP4, Source: repo github.com/PixelML/club-170hx by PixelML on GitHub, posted by @c133, 2026-10-20, and alanoo measured no gain up to NDIV 72 on MoE workloads. Source: @alanoo, 2026-10-14 Most Hynix cards reach NDIV 68-70; 74 fails.

Unlocking

cmpunlocker

The main unlock: an installer that patches NVIDIA's open kernel modules so the card boots with its memory, compute, PCIe Gen2, ECC and BAR1 restored. Linux only, Secure Boot off, rerun after every kernel upgrade. Source: repo github.com/amoghmunikote/cmpunlocker by amoghmunikote on GitHub, posted by @rh3dai, 2026-10-08 Forks add P2P and other patches: cmpunlocker forks. The unlock reaches the card's privileged early boot through a stack overflow, sets the full configuration, backs out, then loads the normal NVIDIA driver. Source: @endsjeremy, 2026-10-27 See Driver unlock.

RIR

Redundancy Information Rows: a small fuse area (8 rows of 32 bits, 16 record slots) that patches bits of the main fuse array at boot. Records are permanent and fuse bits only go from 0 to 1. Source: repo github.com/lixiangwuxian/170hx-rir-tool by lixiangwuxian on GitHub, posted by @lxtend, 2026-10-10 Each record holds a fuse-bit address, a data bit and an enable bit. Source: @_orrorin, 2026-10-10 The 10 GB card ships with all 16 records free; on the 8 GB card 15 are used and the 16th is partly burned. Source: @djpandaman, 2026-10-17 "The RIR burn" means spending two records on a 10 GB card to clear DISABLE_SW_OVERRIDE. Warning A burn cannot be undone. See RIR fuse burn.

DISABLE_SW_OVERRIDE

The fuse (row 0 bit 5, with a copy at row 1 bit 5) that stops software from overriding the other fuses. While it is set, SMs, PCIe speed and memory partitions stay as fused. The 10 GB RIR burn clears it; the 8 GB card has no free record to do so. Source: @lxtend, 2026-10-11

FF, IFF, SW IFF

Fuseless fuse records: configuration written as instructions in the fuse array rather than as single bits. "SW IFF" is the volatile software version, lost on reboot, which is how most 10 GB features are enabled after the burn. Source: @scallion_9883, 2026-10-16

Cap mod (PCIe capacitor mod, x16 mod)

Soldering the missing AC-coupling capacitors (24 small 0402 parts) onto PCIe lanes 4-15 so the card links at x16 instead of x4. Source: repo github.com/amoghmunikote/170th-Street by amoghmunikote on GitHub, posted by @markshowa, 2026-10-18 Needs a microscope and a hot-air station or a fine iron. Source: @cibernox, 2026-10-07 See PCIe capacitor mod.

Links between cards

Gen1, Gen2, Gen3, Gen4

PCIe generations (2.5, 5, 8 and 16 GT/s per lane). The card ships at Gen1 x4. Gen2 is the software link unlock in cmpunlocker: the Gen1 limit was a boot-time setting, not a fuse, so it can be bypassed; Gen3 and Gen4 are fused. Source: @djpandaman, 2026-10-08 Gen2 roughly doubles host transfers, from about 0.85 GB/s to about 1.5 GB/s at x4. Source: repo github.com/ahnguyen17/ga100-fuse-re by ahnguyen17 on GitHub, posted by @exile_1ck, 2026-10-07 Gen3 works only on 10 GB cards after the RIR burn. See Gen2 link retrain and PCIe Gen3 on the 10 GB card.

BAR1

The PCIe window through which the host and other cards see the GPU's memory. Stock it is 64 MiB; cmpunlocker raises it to 64 GiB. Source: repo github.com/amoghmunikote/cmpunlocker by amoghmunikote on GitHub, posted by @rh3dai, 2026-10-08 Some boards and PLX setups cannot fit a 64 GiB BAR in their address space; a P2P mode that works with the 64 MiB BAR exists for them. Source: @ob88594, 2026-10-05 See Resizable BAR and BAR1 64 GB and Platforms.

P2P

Peer-to-peer: one card reading or writing another's memory directly over PCIe instead of through host RAM. It is not on cmpunlocker master; it comes from the maintainer's P2P branch and from Morrowmake's cmpunlocker fork. Source: repo github.com/Morrowmake/cmpunlocker by Morrowmake on GitHub, posted by @trustinter, 2026-10-07 With P2P working, 12 of 12 card pairs reached 5.79 GB/s on one Gen2 x16 PLX host. Source: repo github.com/PixelML/club-170hx by PixelML on GitHub, posted by @c133, 2026-10-20 See P2P.

PLX

PCIe switch chips (Broadcom PEX88096 and similar) that let one CPU slot feed many cards. A 10-port PEX88096 board is a common way to run 4-8 cards with P2P. Source: @djpandaman, 2026-10-22

NVLink

NVIDIA's card-to-card bridge. Fused off and partly depopulated on the 170HX; not public for either version. On PCIe A100-class cards it links pairs only. Source: @endsjeremy, 2026-10-08 See NVLink.

Running models

TP (tensor parallel)

Each layer is split across cards, so every token needs fast card-to-card traffic. It wants x16 links and P2P; the cap mod is "borderline mandatory" for TP=2. Source: @cibernox, 2026-10-13 Gen2 x16 is too slow for TP across mixed cards; a system runs at the speed of its slowest link. Source: @djpandaman, 2026-10-07

PP (pipeline parallel)

Each card holds a block of whole layers and passes activations on. It works on x4 links without P2P, which is why many 8 GB recipes use it. With P2P working, PP still gave better prefill than TP on very long contexts for one 4-card rig. Source: @mountains1605, 2026-10-15 In vLLM the split is set with VLLM_PP_LAYER_PARTITION. Source: @c133, 2026-10-08

EXL3

The ExLlamaV3 quantization format (turboderp). It packs weights as trellis codes that every forward pass must decode with integer math, which is slow on the 170HX: a measured EXL3 matrix multiply used only 6-15% of the card's memory bandwidth, while Marlin INT4 (W4A16) feeds the tensor cores directly and runs fast. Source: @wakeupmbrc1, 2026-10-13

PLE table

The per-layer embedding (n-gram) table of Qwen3.8-Flash-Next, about 30 GB, which recipes move off the GPU to NVMe or RAM to free VRAM. Source: repo github.com/mannydelrio/qwen38-flash-next-2x-cmp170hx by mannydelrio on GitHub, posted by @mrmannyatx, 2026-10-06 "PLE patches" are the engine changes that make this work.

MTP, DFlash2, drafter

Speculative decoding: a small model or extra head (the drafter) guesses several tokens, and the main model checks them in one pass. MTP is the model's own multi-token prediction head; DFlash2 is a separate drafter that guesses up to 7 tokens for one user. Source: repo github.com/Morrowmake/glm53-flash-cmp170hx-recipe by Morrowmake on GitHub, posted by @jjb01957, 2026-10-23 It does not change the output distribution, because the main model verifies every kept token. Source: @greencandle9753, 2026-10-23

Abliterated

A model with its refusal behaviour removed by editing the weights. In use here: the huihui abliteration of Qwen3.8 Flash Next for coding without refusals, Source: @galygious, 2026-10-08 and an abliterated overlay for DeepSeek V4.1 Flash 1017 to stop refusals on reverse-engineering work. Source: @mountains1605, 2026-10-23 Warning Random abliterated merges are one of the attack paths for local AI: a fine-tune can carry hidden triggers. Source: @jjb01957, 2026-10-22

Heretic

Another way to decensor a model; "a heretic run" or "heretic model" is a decensored variant, used much like "abliterated". Example: Phoenix17's Swift-1.5-Qwen3.8-27b-heretic-W8A8-DFlash2, whose model card has 170HX concurrency benchmarks. Source: @phoenixone7, 2026-10-04 With thinking turned on, even his heretic model still deflects some prompts. A recipe page using one: DeepSeek V4.1 Flash heretic on 4x 8 GB. Source: @phoenixone7, 2026-10-25

Morrowmake builds

The engine and recipes by Morrowmake (Discord @voidgiraffe): vllm-cmp170hx, a vLLM plugin with sm_80 kernels plus a short patch queue pinned to an upstream vLLM commit, and recipe repos for GLM-5.3-Flash and DeepSeek-V4.1-Flash on four cards and Qwen3.8-Flash-Next on two. Source: repo github.com/Morrowmake/vllm-cmp170hx by Morrowmake on GitHub, posted by @voidgiraffe, 2026-10-15 His P2P driver build is the Morrowmake cmpunlocker fork. "Marrow's build" on the Discord means the same thing. Source: @mountains1605, 2026-10-06 The GLM 5.3 Flash recipe is the community's daily driver on 4 cards. See GLM 5.3 Flash on 4x 8 GB, DeepSeek V4.1 Flash on 4x 8 GB (Morrowmake) and Recipes.

Strata

An inference engine that keeps the hottest MoE experts in VRAM and the rest in system RAM, nearly lossless versus all-GPU experts. Source: @wakeupmbrc1, 2026-10-07

Tools and slang

170tune

Tuning tool for the HBM clock (NDIV), core clock offset, power limit and memory timings. Its preflight checks that the unlock opened the registers it writes. See Tools.

gpcprobe

A read-only kernel module that reads the floorsweep fuses with the NVIDIA driver loaded: which GPCs, FBPs and FBPAs are enabled, disabled or defective. Source: repo github.com/matstatman/gpcprobe by matstatman on GitHub, posted by @matstatman, 2026-10-20 See Monitoring.

Xid

NVIDIA driver error codes in dmesg. Common here: Xid 31 (instability after an undervolt), Source: @wakeupmbrc1, 2026-10-12 Xid 109 (context switch timeout, seen with defective GPCs enabled), Source: @lxtend, 2026-10-17 Xid 79 (fallen off the bus, needs a full power cycle). Source: repo github.com/PixelML/club-170hx by PixelML on GitHub, posted by @c133, 2026-10-20 See Xid errors.

Clanker

Discord slang for an AI coding agent, as in "my clanker found out". Source: @markshowa, 2026-10-26

Pearl (PRL)

A cryptocurrency some owners mine on the cards when they are not serving models; 12 cards mining only at night were reported to earn about 700 USD a month. Source: @reala7096, 2026-10-23