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Drilldown: Recipe

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Recipe > card count: 2-4 & source : https://github.com/alexvnesta/glm53-flash-cmp170hx-tp or Other

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quant:
AWQ INT4: cyankiwi/Qwen3.8-Flash-Next-AWQ-INT4; 95 GiB BF16 PLE table in host RAM (FP8 table optional) (1) · AWQ W4A16 g32 (leoncca/Qwen3.8-Flash-Next-Uncensored-AWQ-g32); PLE table converted to INT4 and served from SSD (1) · AWQ W4A16: wtdcode/Qwen3.8-Flash-Next-AWQ-W4A16 (1) · EXL3 3.05 bpw: turboderp/GLM-5.3-Flash-exl3 (1) · EXL3 3.05 bpw: turboderp/GLM-5.3-Flash-exl3; DFlash2 drafter converted to EXL3 6 bpw (1) · EXL3 3.5 bpw (LibertAIDAI; routed experts 4 bpw on layers 0-9 and 30-39, 3 bpw on 10-29; attention and shared experts 6 bpw) plus the official Engram shards (1) · EXL3 4 bpw (Mia-AiLab/GLM-5.3-Flash-EXL3-TR3-4bpw, 164 GB) plus an offline-generated Marlin INT4 decode sidecar (151 GB) (1) · EXL3 5.05 bpw; PLE (n-gram) table read from SSD (1) · Hybrid: all 40 expert layers at 3 bits (LibertAI 2.9 bpw pack with layers 18-22 grafted from the 3.5 bpw pack), official FP8 dense tensors (1) · Hybrid: LibertAI EXL3 2.9 bpw routed experts (layers 0-39), official FP8/FP4 for attention, shared experts, head, draft and Engram; KV fp8_ds_mla (1) · Hybrid: routed experts EXL3 (mostly 3 bpw, 2 bpw on layers 18-22) from LibertAI's 2.9 bpw pack; attention, shared experts, indexer and DSpark drafter official FP8; KV fp8_ds_mla (1) · Hybrid: routed experts EXL3 2.9 bpw (LibertAIDAI), everything else official FP8/BF16 with the 38 heretic attn.wo_b tensors (1) · Hybrid: routed experts EXL3 2.9 bpw (LibertAIDAI), everything else official FP8/BF16; KV BF16 (1) · Maya GGUF (Maya-S 340 GB or Maya-XS 277 GB; Engram tables stay on SSD) (1) · Maya-M GGUF (116 GB), every expert in VRAM; Maya-S (96.5 GB) and Maya-S24 (94.7 GB) also reported (1) · Mixed INT4 AutoRound (Minachist/Qwen3.8-Flash-Next-INT4-Mixed-AutoRound, about 65 GB) with the full BF16 PLE table on NVMe (1) · Native MXFP4 experts + FP8 attention (official deepseek-ai checkpoint, about 155.4 GiB); KV cache fp8 (2) · NVFP4 (ModelOpt mixed precision): ProCreations/MiMo-V2.6-Flash-RL-NVFP4, run as 4-bit weights with BF16 activations through Marlin (1) · NVFP4 main weights through Marlin (no native FP4 on sm_80), mixed FP8 and BF16 MTP weights, FP8 PLE table (about 51.2 GB) kept on NVMe (1) · Official block FP8, about 126 GiB including the about 50 GiB FP8 n-gram (PLE) table, which is served from host RAM; KV cache bf16 (the QSA layers refuse fp8) (1) · W4A16 (INT4 weights, group size 128, FP16 activations): canada-quant/GLM-5.3-Flash-W4A16-MTP (1) · W4A16 AutoRound: Intel/Qwen3.8-Flash-Next-W4A16-AutoRound; 95.4 GiB BF16 PLE table streamed from NVMe; KV fp8 e4m3 (software-decoded on SM80) (1) · W4A16 INT4 g128 with the PLE table repacked INT4 g32: zankich/Qwen3.8-Flash-Next-W4A16-Merlin-INT4PLE-FP8KV; KV BF16 (1) · W4A16, about 4.3 bpw, 163 GiB on disk (1) · W4A16: halt95/Qwen3.8-Flash-Next-W4A16-Merlin (AutoRound INT4 g128 experts, INT8 GDN projections, FP8 n-gram table) (1)
engine:
ExLlamaV3 (patched, pinned) (1) · ExLlamaV3 1.5.4 (built for SM80) with a small OpenAI-compatible server (1) · ExLlamaV3 fork (anoane/exllamav3-anemone) + TabbyAPI fork (anoane/tabbyAPI) (1) · GNmac-lab recipe image 1.2.0 (vLLM with sm_80 patches) plus three patches (1) · Morrowmake/vllm-cmp170hx (bind-mounted sm80 package) plus the author's tensor-core MoE kernels (1) · Morrowmake/vllm-cmp170hx (EXL3 path) (1) · Morrowmake/vllm-cmp170hx (via the glm53-flash-cmp170hx-recipe) (1) · Morrowmake/vllm-cmp170hx (vLLM fork, container image) (3) · Morrowmake/vllm-cmp170hx image (Qwen EXL3 release) with patch files mounted read-only (1) · Morrowmake/vllm-cmp170hx image (tag qwen38-recipe-1.0.0) plus one mounted file (vLLM #58235 vision-sink fix) (1) · Project Maya (Strata and llama.cpp lineage) (1) · Project Maya (Strata and llama.cpp lineage, EXL3 loading, DFlash2 drafter) (1) · Qwen-Flash-SM80 overlay on vllm/vllm-openai:qwen38-flash-next (digest-pinned), FlashInfer PCIe IPC AllReduce, GDS/cuFile over NVMe P2PDMA (1) · vLLM 0.29.1rc1 nightly plus the checkpoint author's patches (1) · vLLM nightly + PR #53899 (a5530b9) + the repo's patch scripts (1) · vLLM nightly 7d0b4e57 plus the author's pure-Python fork clee/vllm-sm80 (branch q38fn/stack) (1) · vLLM v0.30.0 + zankich INT4-PLE plugin + six hash-guarded patch layers (1) · vLLM with a pinned sm_80 patch stack (built locally from source) (1) · vLLM: haosdent/vllm branch dsv4-flash-a100 plus allover326's 7 patches (DSpark under PP, sm_80 prefill top-k fallback, logits row chunking) (1) · vLLM: haosdent/vllm branch dsv4-flash-a100 with a vendored copy of allover326's 7 patches (image dsv4-a100:devel) (1) · vLLM: hyd998877/vllm_170hx_glm53-flash-exl3-optimized with kaka86mm's overlay patches; exllamav3 1.4.8 (1) · vLLM: the vllm/vllm-openai:qwen38-flash-next image with zebgop-ops patches 0001 to 0016 (never 0008-WITHDRAWN) and three ported files (1) · wtdcode/vllm-backport (image lazymio/vllm-backport:latest-sm80) (1) · wtdcode/vllm-backport 3142ded1 plus a two-file patch and two tinybeast PLE plugins (venv, no container) (1)
cards:
card count:
topology:
engine-managed expert tiering across VRAM, host RAM and NVMe (1) · engine-managed split with expert tiering across VRAM, RAM and NVMe (1) · layer split (no tensor parallel), no P2P (1) · PP2 (layer partition 25,23), no P2P (1) · PP2 with PLE CPU offload (1) · PP2, MTP 3, no P2P (1) · PP2, MTP depth 3 (1) · PP3 (1) · PP3 (VLLM_PP_LAYER_PARTITION=15,15,13) with DSpark, 5 draft tokens; PCIe Gen2 x4, no P2P (1) · PP3, no P2P (works at PP2 on two cards) (1) · PP4 (VLLM_PP_LAYER_PARTITION=12,12,12,7) with DSpark, 5 draft tokens; PCIe Gen2 x4, no P2P (1) · PP4 (VLLM_PP_LAYER_PARTITION=13,11,11,10), DFlash2 k=7; PCIe Gen2 x4, no P2P (1) · PP4, VLLM_PP_LAYER_PARTITION=12,12,12,12, MTP 3, FULL_AND_PIECEWISE CUDA graphs; PCIe Gen2 x4 per card, no P2P. Three cards: PP3 with 16,17,15 or 16,16,16 (1) · TEP2 (TP2 plus expert parallel), MTP 6; one card at PCIe Gen2 x16 (x16 mod), one at Gen2 x4; GPU P2P required (1) · TP2 over NCCL (GPU P2P), DFlash2 K7 plus hybrid drafting (1) · TP2 with expert parallel (1) · TP2 with whole-expert expert parallel (1) · TP4 (1) · TP4 (default) or PP4 (1) · TP4 (default) or PP4 for x1/x4 links (1) · TP4 (P2P on); expert parallel off (1) · TP4 with expert parallel (96 whole experts per card) (1) · TP4 with expert parallel, MTP 3 (1) · TP4, P2P on (1) · TP4, peer access off (NCCL_P2P_DISABLE=1), host all-reduce (1) · TP5 across four CMP 170HX and one RTX PRO 6000 Blackwell (native backend, reduces through host memory); MTP draft on the PRO (1)
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