PCIe Gen3 on the 10 GB card: Difference between revisions

Latest revision as of 10:02, 30 October 2026

PCIe Gen3 link (10 GB card)
Proven 10 GB
Driver	nvidia-open 615.71.09 (reference) / 610.43.03
Unlock build	lixiangwuxian/170hx_tips + 170hx-rir-tool
Steps	PCIe Gen3 on the 10 GB card
Source	link
Confirmations	Reproduced by @djpandaman (10 GB), 2026-10-11 · details

Warning 10 GB card only. It needs the permanent RIR fuse burn first. The 8 GB card cannot reach Gen3: its Gen3-disable fuse register is locked and there is no free RIR to clear it (see below).

Why the 8 GB card is stuck at Gen2

Gen3 and Gen4 are real fuses (OPT_DISABLE_GEN3_SPEED, OPT_PCIE_BOOT_GEN3_DISABLE), unlike the Gen2 bootstrap bypass. You cannot retrain at 8 GT/s with the disable fuse set. Source: @djpandaman, 2026-10-08 On the 8 GB card that fuse register is locked and there is no spare RIR to clear it, so Gen3 "retrain" is blocked. Source: @wakeupmbrc1, 2026-10-25
Source: @wakeupmbrc1, 2026-10-25 A probe on a 10 GB card confirms all three Gen3 fuses read 1 at stock (OPT_DISABLE_GEN3_SPEED=1, OPT_PCIE_BOOT_GEN23_DISABLE=1, OPT_PCIE_BOOT_GEN3_DISABLE=1), which is why the gate must be opened first. Source: @darkshad03, 2026-10-04

Prerequisites

10 GB card (10de:2082), RIR fuse burn done (disable_sw_override cleared).
A working cmpunlocker-style driver already initialising the card (this does not do the memory

 unlock).

Reference driver nvidia-open 615.71.09 (the guide's), or 610.43.03 (the evanrodgers wrapper's).

Steps (lixiangwuxian/170hx_tips)

The process lives in Gen3_unlock_en.md (@lxtend). It has three parts: a probe-time fuse software override, a post-GSP Gen3 register sequence inside the driver, and RM link training. Only LnkSta: Speed 8GT/s counts as success, not LnkCap or LnkCtl2. The guide itself does not say it is for the 10 GB card only; that is stated in the 170hx_tips README (@alanoo asked for it to be added to the doc, @lxtend pointed to the README). Source: @alanoo, 2026-10-19
Source: @lxtend, 2026-10-19

Module parameters (merge into your existing config, keep one value per key):

options nvidia NVreg_RegistryDwords="RmForceEnableGen2=1;RMPcieLinkSpeed=0x5;CmpGen3=1" cmp_fuse_gen3=0

RMPcieLinkSpeed=0x5 is a bitfield that allows Gen3; it does not mean "generation five". CmpGen3 is a custom registry key read by the patch. cmp_fuse_gen3 is not a stock NVIDIA parameter, so you must build the patched module that defines it; adding it to a stock driver does nothing. For Gen3, set only cmp_fuse_gen3=0; do not also set cmp_fuse_gpc=0, cmp_fuse_tpc*=0 or cmp_fuse_flr=1.

Key registers the patch touches (BAR0): EN_SW_OVERRIDE 0x00820040, DISABLE_SW_OVERRIDE 0x00820084, OPT_DISABLE_GEN3_SPEED 0x00820250 bit 0, OPT_PCIE_BOOT_GEN3_DIS 0x00820580 bit 0. The post-GSP Gen3 block sits in kgspBootstrap_TU102, gated on device id 0x2082 and CmpGen3=1, and finishes with a Gen1 to Gen2 to Gen3 retrain via the RM control NV2080_CTRL_CMD_BUS_SET_PCIE_SPEED (0x20801805, a 4-byte generation value, not MB/s).

Rollback: cmp-pcie-speed 2 returns to Gen2 at runtime; setting CmpGen3=0 is not a runtime undo. Full write-up and the ready-made wrapper: [https://github.com/evanrodgers/cmp-170hx-rir-burn-util evanrodgers/cmp-170hx-rir-gen3], which validated Gen3 x4 at boot on two cards with a 30-minute clean stress run.

Numbers / state

lxwx got Gen3 working on a 10 GB card on 2026-10-12 (his slot is x4, so Gen3 x4 equals Gen1 x16 bandwidth; his board

 is PCIe 3.0, so Gen4 was untested). Source: @lxtend, 2026-10-12

mrpandagod has done Gen3 and Gen4 on 10 GB cards via the RIR route.

 Source: @djpandaman, 2026-10-11

Gen4 behind a PLX switch was validated by mrpandagod (his motherboard is only Gen3).

 Source: @djpandaman, 2026-10-09

x16 width needs the capacitor mod. Without the caps, Gen4 falls back to 8.0 GT/s (Gen3).

 Source: @djpandaman, 2026-10-08

Known issues

Warning A Gen3 transition lost a card on one machine (RM 0x0f, fell off the bus); recover with a reboot or

 power cycle. That card's PCIe controller was later judged physically damaged. (170hx_tips Validation record.)

The guide was validated only on the 10 GB card (10de:2082); 10de:20c2 is untested and

 blocked anyway.

On 170hx-rir-tool the volatile --sw-write gen3 0 opens the fuse bits but the link can stay

 at Gen2; most overrides must happen at init/boot, which is why the driver-side patch is needed.
 Source: @lxtend, 2026-10-11

Contested whether Gen3 is consistent enough across cards to call "unlocked"; some think it needs a soldering iron or

 will not generalise. Source: @dany0_, 2026-10-07

Contested The GitHub record and the chat disagree, in the order posted:
- Consensus-Protocol's Gen3/Gen4 write-up (as of 2026-07-28): no Gen3 or Gen4 link has ever trained on a CMP 170HX. Gen3 could be advertised (LnkCap 8 GT/s, target 8 GT/s accepted) while LnkSta stayed at 2.5 GT/s; both Gen fuses (0x0082057c, 0x00820580) read 1 and the write to 0x0082057c fails. These attempts predate the 10 GB RIR route. Source: repo github.com/Consensus-Protocol/cmp170hx by Consensus-Protocol on GitHub, posted by @rrickk420, 2026-10-09
- After the RIR burn, lxwx, mrpandagod and evanrodgers report Gen3 links (above); the evanrodgers README records LnkSta 8 GT/s on both ends for two cards. A post-burn fuse read plus LnkSta from more owners would settle it. Source: repo github.com/evanrodgers/cmp-170hx-rir-burn-util by evanrodgers on GitHub, posted by @hezz1891, 2026-10-26
replacedriver47's earlier attempt (cmp170hx-gen3-summary.md, AI-drafted, superseded by lxwx's

 working guide): it proposed bringing up Gen3/Gen4 through the same XCE/CYA PCIe port-controller registers the Gen2
 unlock uses. ropuls corrected it: LINK_CONFIG_0 (0x8c040) MAX_LINK_RATE[19:18]
 uses NVIDIA's reversed encoding (0 = Gen4, 1 = Gen3, 2 = Gen2, 3 = Gen1), so Gen3 is value 1, not 2. It was never
 shown to train a link. Source: @replacedriver47, 2026-10-08

 Source: @ropuls, 2026-10-08

Status

Reproduced on more than one 10 GB card (lxwx, then mrpandagod and evanrodgers independently), so Proven on the 10 GB card. See the confirmation below.

@@ Line 19: / Line 19: @@
 {{Source|djpandaman|2026-10-08|https://discord.com/channels/1518634379604136178/1518695328008638516/1557879842152648776}}
 On the 8 GB card that fuse register is locked and there is no spare RIR to clear it, so Gen3 "retrain" is blocked.
-{{Source|wakeupmbrc1|2026-10-18|https://discord.com/channels/1518634379604136178/1518695328008638516/1563810876778217483}}
+{{Source|wakeupmbrc1|2026-10-25|https://discord.com/channels/1518634379604136178/1518695328008638516/1563815547462881323}}<br />
+{{Source|handle=wakeupmbrc1|date=2026-10-25|link=https://discord.com/channels/1518634379604136178/1518695328008638516/1563815629469777931}}
 A probe on a 10 GB card confirms all three Gen3 fuses read 1 at stock (<code>OPT_DISABLE_GEN3_SPEED=1</code>,
 <code>OPT_PCIE_BOOT_GEN23_DISABLE=1</code>, <code>OPT_PCIE_BOOT_GEN3_DISABLE=1</code>), which is why the gate must be
@@ Line 36: / Line 37: @@
 (@lxtend). It has three parts: a probe-time fuse software override, a post-GSP Gen3 register sequence inside the driver,
 and RM link training. Only <code>LnkSta: Speed 8GT/s</code> counts as success, not LnkCap or LnkCtl2.
+The guide itself does not say it is for the 10 GB card only; that is stated in the 170hx_tips README (@alanoo asked
+for it to be added to the doc, @lxtend pointed to the README).
+{{Source|handle=alanoo|date=2026-10-19|link=https://discord.com/channels/1518634379604136178/1518695328008638516/1561660485412192267}}<br />
+{{Source|handle=lxtend|date=2026-10-19|link=https://discord.com/channels/1518634379604136178/1518695328008638516/1561661562681303041}}
 Module parameters (merge into your existing config, keep one value per key):
@@ Line 81: / Line 86: @@
 * Contested whether Gen3 is consistent enough across cards to call "unlocked"; some think it needs a soldering iron or
    will not generalise. {{Source|dany0_|2026-10-07|https://discord.com/channels/1518634379604136178/1528513735575081070/1557398054985011281}}
+* {{Status|Contested}} The GitHub record and the chat disagree, in the order posted:
+** Consensus-Protocol's Gen3/Gen4 write-up (as of 2026-07-28): no Gen3 or Gen4 link has ever trained on a CMP 170HX. Gen3 could be advertised (<code>LnkCap</code> 8 GT/s, target 8 GT/s accepted) while <code>LnkSta</code> stayed at 2.5 GT/s; both Gen fuses (<code>0x0082057c</code>, <code>0x00820580</code>) read 1 and the write to <code>0x0082057c</code> fails. These attempts predate the 10 GB RIR route. {{Source|handle=rrickk420|date=2026-10-09|link=https://discord.com/channels/1518634379604136178/1518692084729511967/1558127650223030302|repo=https://github.com/Consensus-Protocol/cmp170hx}}
+** After the RIR burn, lxwx, mrpandagod and evanrodgers report Gen3 links (above); the evanrodgers README records <code>LnkSta</code> 8 GT/s on both ends for two cards. A post-burn fuse read plus <code>LnkSta</code> from more owners would settle it. {{Source|handle=hezz1891|date=2026-10-26|link=https://discord.com/channels/1518634379604136178/1518692084729511967/1564222043363352576|repo=https://github.com/evanrodgers/cmp-170hx-rir-burn-util}}
 * '''replacedriver47's earlier attempt''' (<code>cmp170hx-gen3-summary.md</code>, AI-drafted, superseded by lxwx's
    working guide): it proposed bringing up Gen3/Gen4 through the same XCE/CYA PCIe port-controller registers the Gen2