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single card ·
engine-managed expert tiering across VRAM, host RAM and NVMe ·
engine-managed split with expert tiering across VRAM, RAM and NVMe ·
layer split (no tensor parallel), no P2P ·
PP2 (layer partition 25,23), no P2P ·
PP2 with PLE CPU offload ·
PP2, MTP 3, no P2P ·
PP2, MTP depth 3 ·
PP3 ·
PP3 (VLLM_PP_LAYER_PARTITION=15,15,13) with DSpark, 5 draft tokens; PCIe Gen2 x4, no P2P ·
PP3, no P2P (works at PP2 on two cards) ·
PP4 (VLLM_PP_LAYER_PARTITION=12,12,12,7) with DSpark, 5 draft tokens; PCIe Gen2 x4, no P2P ·
PP4 (VLLM_PP_LAYER_PARTITION=13,11,11,10), DFlash2 k=7; PCIe Gen2 x4, no P2P ·
PP4, VLLM_PP_LAYER_PARTITION=12,12,12,12, MTP 3, FULL_AND_PIECEWISE CUDA graphs; PCIe Gen2 x4 per card, no P2P. Three cards: PP3 with 16,17,15 or 16,16,16 ·
PP5 with an even 8,8,8,8,8 layer split; the repo's cards are on PCIe Gen2 x16 with no NVLink ·
PP8 (also PP9 and PP10), TP1 ·
PP8 (VLLM_PP_LAYER_PARTITION=7,5,7,5,7,5,7,2) with DFlash2, 7 draft tokens; PCIe Gen2 x4, no P2P; host 2x Xeon E5-2690 v4, 96 GB DDR4 ·
PP8, partition 5,5,5,5,5,5,5,5 ·
PP8, TP1 ·
TEP2 (TP2 plus expert parallel), MTP 6; one card at PCIe Gen2 x16 (x16 mod), one at Gen2 x4; GPU P2P required ·
TP2 over NCCL (GPU P2P), DFlash2 K7 plus hybrid drafting ·
TP2 with expert parallel ·
TP2 with whole-expert expert parallel ·
TP2 x PP3, partition 14,14,12 ·
TP4 ·
TP4 (default) or PP4 ·
TP4 (default) or PP4 for x1/x4 links ·
TP4 (P2P on); expert parallel off ·
TP4 with expert parallel (96 whole experts per card) ·
TP4 with expert parallel, MTP 3 ·
TP4 x PP2, partition 20,20 ·
TP4, P2P on ·
TP4, peer access off (NCCL_P2P_DISABLE=1), host all-reduce ·
TP5 across four CMP 170HX and one RTX PRO 6000 Blackwell (native backend, reduces through host memory); MTP draft on the PRO ·
TP6 (virtual-head padding), PP1 ·
Other ·
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