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Morrowmake/vllm-cmp170hx (vLLM fork, container image) ·
vLLM PR #56201 head (79a7108d) plus the two Deepinfer-SM80 patches and 30 drop-in modules ·
Custom SM80 vLLM (patched from public commit 79a7108d9) ·
ExLlamaV3 (patched, pinned) ·
ExLlamaV3 1.5.4 (built for SM80) with a small OpenAI-compatible server ·
ExLlamaV3 fork (anoane/exllamav3-anemone) + TabbyAPI fork (anoane/tabbyAPI) ·
GNmac-lab recipe image 1.2.0 (vLLM with sm_80 patches) plus three patches ·
Morrowmake/vllm-cmp170hx (bind-mounted sm80 package) plus the author's tensor-core MoE kernels ·
Morrowmake/vllm-cmp170hx (EXL3 path) ·
Morrowmake/vllm-cmp170hx (via the glm53-flash-cmp170hx-recipe) ·
Morrowmake/vllm-cmp170hx branch ampere-glm53 plus fail-closed source patches ·
Morrowmake/vllm-cmp170hx image (Qwen EXL3 release) with patch files mounted read-only ·
Morrowmake/vllm-cmp170hx image (tag qwen38-recipe-1.0.0) plus one mounted file (vLLM #58235 vision-sink fix) ·
Morrowmake/vllm-cmp170hx image with patch files mounted read-only ·
Project Maya (Strata and llama.cpp lineage) ·
Project Maya (Strata and llama.cpp lineage, EXL3 loading, DFlash2 drafter) ·
Qwen-Flash-SM80 overlay on vllm/vllm-openai:qwen38-flash-next (digest-pinned), FlashInfer PCIe IPC AllReduce, GDS/cuFile over NVMe P2PDMA ·
vLLM ·
vLLM (build not stated) ·
vLLM 0.29.1rc1 nightly plus the checkpoint author's patches ·
vLLM a5a30471 plus a 13-file downstream patch (native Linux AIO PLE reader) ·
vLLM nightly + PR #53899 (a5530b9) + the repo's patch scripts ·
vLLM nightly 7d0b4e57 plus the author's pure-Python fork clee/vllm-sm80 (branch q38fn/stack) ·
vLLM PR #56201 head (79a7108d) plus a 20-patch sm_80 series; image zanooda/vllm-sm80-ds41f:v41-sm80 ·
vLLM v0.30.0 + zankich INT4-PLE plugin + six hash-guarded patch layers ·
vLLM with a pinned sm_80 patch stack (built locally from source) ·
vLLM: 344303947's fork of wtdcode/vllm-backport (shadow source layer, staged Marlin repack, exact-size Engram pinning) ·
vLLM: haosdent/vllm branch dsv4-flash-a100 plus allover326's 7 patches (DSpark under PP, sm_80 prefill top-k fallback, logits row chunking) ·
vLLM: haosdent/vllm branch dsv4-flash-a100 with a vendored copy of allover326's 7 patches (image dsv4-a100:devel) ·
vLLM: hyd998877/vllm_170hx_glm53-flash-exl3-optimized with kaka86mm's overlay patches; exllamav3 1.4.8 ·
vLLM: official vllm/vllm-openai:glm53-flash image plus promisezackr's 24 patches (SM8x base from 344303947/vllm170hx, pipeline parallel for GLM-5.3-Flash, DFlash2 under PP8) ·
vLLM: the vllm/vllm-openai:qwen38-flash-next image with zebgop-ops patches 0001 to 0016 (never 0008-WITHDRAWN) and three ported files ·
wtdcode/vllm-backport (image lazymio/vllm-backport:latest-sm80) ·
wtdcode/vllm-backport 3142ded1 plus a two-file patch and two tinybeast PLE plugins (venv, no container) ·
Other ·
None
engine version:
cards:
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single card ·
engine-managed expert tiering across VRAM, host RAM and NVMe ·
engine-managed split with expert tiering across VRAM, RAM and NVMe ·
layer split (no tensor parallel), no P2P ·
PP2 (layer partition 25,23), no P2P ·
PP2 with PLE CPU offload ·
PP2, MTP 3, no P2P ·
PP2, MTP depth 3 ·
PP3 ·
PP3 (VLLM_PP_LAYER_PARTITION=15,15,13) with DSpark, 5 draft tokens; PCIe Gen2 x4, no P2P ·
PP3, no P2P (works at PP2 on two cards) ·
PP4 (VLLM_PP_LAYER_PARTITION=12,12,12,7) with DSpark, 5 draft tokens; PCIe Gen2 x4, no P2P ·
PP4 (VLLM_PP_LAYER_PARTITION=13,11,11,10), DFlash2 k=7; PCIe Gen2 x4, no P2P ·
PP4, VLLM_PP_LAYER_PARTITION=12,12,12,12, MTP 3, FULL_AND_PIECEWISE CUDA graphs; PCIe Gen2 x4 per card, no P2P. Three cards: PP3 with 16,17,15 or 16,16,16 ·
PP5 with an even 8,8,8,8,8 layer split; the repo's cards are on PCIe Gen2 x16 with no NVLink ·
PP8 (also PP9 and PP10), TP1 ·
PP8 (VLLM_PP_LAYER_PARTITION=7,5,7,5,7,5,7,2) with DFlash2, 7 draft tokens; PCIe Gen2 x4, no P2P; host 2x Xeon E5-2690 v4, 96 GB DDR4 ·
PP8, partition 5,5,5,5,5,5,5,5 ·
PP8, TP1 ·
TEP2 (TP2 plus expert parallel), MTP 6; one card at PCIe Gen2 x16 (x16 mod), one at Gen2 x4; GPU P2P required ·
TP2 over NCCL (GPU P2P), DFlash2 K7 plus hybrid drafting ·
TP2 with expert parallel ·
TP2 with whole-expert expert parallel ·
TP2 x PP3, partition 14,14,12 ·
TP4 ·
TP4 (default) or PP4 ·
TP4 (default) or PP4 for x1/x4 links ·
TP4 (P2P on); expert parallel off ·
TP4 with expert parallel (96 whole experts per card) ·
TP4 with expert parallel, MTP 3 ·
TP4 x PP2, partition 20,20 ·
TP4, P2P on ·
TP4, peer access off (NCCL_P2P_DISABLE=1), host all-reduce ·
TP5 across four CMP 170HX and one RTX PRO 6000 Blackwell (native backend, reduces through host memory); MTP draft on the PRO ·
TP6 (virtual-head padding), PP1 ·
Other ·
None
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single card