PEX9797 management lane on the 4028GR-TRT2 (probably unwired; FPGA coordinator idea); PEX88096 SBR per-slot bifurcation image diff (about 8 bytes)

Swimlane: Default swimlane
Column: Researching
Position: 9

Description

Reported by / on it: @markshowa, @peter643, @cibernox

Source: https://oshwhub.com https://github.com/xiaowine/chip-docs

Wiki page: Risers and bifurcation

Cards: both

Card D-063, seeded from the cmpunlocker Discord with credit (reference github:xiaowine/chip-docs).

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