ImportBot: The PCIe Gen2 link enable that ships in cmpunlocker and the early-boot retrain hammer; x16 needs the capacitor mod; sources are cmpunlocker and the Discord Oct 2026.; sources: @_j3ns, @djpandaman, @rrickk420, @wakeupmbrc1, @robbbbbb7973; GitHub Consensus-Protocol/cmp170hx, amoghmunikote/cmpunlocker

2026-10-30T10:02:11Z

The PCIe Gen2 link enable that ships in cmpunlocker and the early-boot retrain hammer; x16 needs the capacitor mod; sources are cmpunlocker and the Discord Oct 2026.; sources: @_j3ns, @djpandaman, @rrickk420, @wakeupmbrc1, @robbbbbb7973; GitHub Consensus-Protocol/cmp170hx, amoghmunikote/cmpunlocker

← Older revision		Revision as of 10:02, 30 October 2026
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	Link '''speed''' (Gen1 to Gen2) and link '''width''' (x4 to x16) are separate problems. Gen2 is software; x16 width		Link '''speed''' (Gen1 to Gen2) and link '''width''' (x4 to x16) are separate problems. Gen2 is software; x16 width
	needs the hardware [[Cooling and power\|capacitor mod]] on lanes 4-15. Without the caps the maximum width is x4.		needs the hardware [[Cooling and power\|capacitor mod]] on lanes 4-15. Without the caps the maximum width is x4.
	{{Source\|djpandaman\|2026-10-16\|https://discord.com/channels/1518634379604136178/1518692084729511967/~~1560681653788217435~~}}		{{Source\|handle=djpandaman\|date=2026-10-17\|link=https://discord.com/channels/1518634379604136178/1518692084729511967/1561021502739189892}}

	== How it works ==		== How it works ==

ImportBot: The PCIe Gen2 link enable that ships in cmpunlocker and the early-boot retrain hammer; x16 needs the capacitor mod; sources are cmpunlocker and the Discord Oct 2026.; sources: @_j3ns, @djpandaman, @rrickk420, @wakeupmbrc1, @robbbbbb7973; GitHub Consensus-Protocol/cmp170hx, amoghmunikote/cmpunlocker

2026-10-30T08:04:19Z

New page

{{Unlock
|unlocks=PCIe Gen2 link speed
|variant=both
|driver_version=nvidia-open 610.43.02 to 615.71.10
|unlock_build=amoghmunikote/cmpunlocker v0.5
|steps_page=Gen2 link retrain
|status=Reported
|tested_by=_j3ns
|source=https://github.com/amoghmunikote/cmpunlocker
}}

The stock CMP 170HX links at PCIe '''Gen1'''. [[Driver unlock|cmpunlocker]] raises it to '''Gen2''' on both cards. This
is pure software (no fuse burn) and is the ceiling the mainline repo claims; Gen3 is a separate, 10 GB-only story (see
[[PCIe Gen3 on the 10 GB card]]). Gen2 alone is a 2x bandwidth step over stock Gen1.

Link '''speed''' (Gen1 to Gen2) and link '''width''' (x4 to x16) are separate problems. Gen2 is software; x16 width
needs the hardware [[Cooling and power|capacitor mod]] on lanes 4-15. Without the caps the maximum width is x4.
{{Source|djpandaman|2026-10-16|https://discord.com/channels/1518634379604136178/1518692084729511967/1560681653788217435}}

== How it works ==

The silicon was never fused to Gen1; Amogh's Gen2 enable bypasses a bootstrap by writing XVE_FUSE_OVERRIDE =
<code>0x6</code>, which lets LINK_CAP reach Gen2. There is no physical Gen2-disable fuse (unlike Gen3/Gen4, which are
real fuses). {{Source|djpandaman|2026-10-09|https://discord.com/channels/1518634379604136178/1518695328008638516/1557999353052794941}}

Two pieces in cmpunlocker do it:

* <code>pcie-gen2.patch</code> sets the PL link-rate register <code>0x0008c1c0 = 0x00240036</code> and the related fuse
override / XP3G registers; <code>pcie-gen2-probe-retrain.patch</code> handles the retrain.
* An '''early-boot retrain service''' (<code>gen2.service</code>, runs <code>/usr/local/sbin/gen2-hammer</code>). The
Gen2 advertisement window opens for only a fraction of a second when the initramfs-loaded module's booter writes land,
before any normal systemd unit runs, so the hammer loops <code>setpci CAP_EXP+12</code> on the bridge and GPU (default
600 iterations at 0.05 s) to catch it. {{Source|rrickk420|2026-08-22|https://github.com/Consensus-Protocol/cmp170hx}}

The install writes <code>/etc/modprobe.d/cmp-pcie-gen2.conf</code>:

<syntaxhighlight lang="text">
options nvidia NVreg_RegistryDwords="RmForceEnableGen2=1;RMPcieLinkSpeed=0x1"
</syntaxhighlight>

== Verify ==

<syntaxhighlight lang="bash">
nvidia-smi --query-gpu=pcie.link.gen.current,pcie.link.gen.max --format=csv # expect 2,2
sudo ./tools/service.sh verify # cmpunlocker helper
setpci -s <bdf> CAP_EXP+12.w # 0x1042 = Gen2 x4, 0x1041 = Gen1
sudo lspci -s <bdf> -vvv | grep LnkSta
</syntaxhighlight>

Judge Gen2 by <code>setpci CAP_EXP+12</code> or <code>lspci LnkSta</code>, not by
<code>nvidia-smi pcie.link.gen.current</code>, which can still report 1 after a successful catch. Recovery boot option
if the service misbehaves: <code>systemd.mask=gen2.service</code>.

== Numbers ==

Gen2 x4 measured about 1.5 GB/s each way, up from about 0.85 GB/s at Gen1 (roughly 1.8x). With the x16 capacitor mod,
Gen2 x16 reached about 6.63-6.67 GB/s. {{Source|rrickk420|2026-08-22|https://github.com/Consensus-Protocol/cmp170hx}}
P2P over native Gen2 x16 slots is about the same latency as a crossbar, around 1.5 us per transaction; switches add
latency. {{Source|wakeupmbrc1|2026-10-17|https://discord.com/channels/1518634379604136178/1518692084729511967/1561016069248917585}}

== Known issues ==

* '''Gen2 does not train under VFIO passthrough''' in some setups (Consensus-Protocol notes); and on 615.78.08 several
people saw Gen2 training fail and the cards drop off <code>nvidia-smi</code> (see [[Driver unlock]]).
* '''x4 after the cap mod:''' continuity faults on one lane pair drop the width; reflow the suspect caps and check with a
DMM. A card that failed the mod still works at x4. See [[Cooling and power]] for the mod and troubleshooting.
* ASPM idle link-speed drop (Gen2 to Gen1 at idle) to save power is an untested idea; nvidia-smi only guesses the link
state, <code>lspci</code> shows the truth. {{Source|robbbbbb7973|2026-10-21|https://discord.com/channels/1518634379604136178/1534543856006332586/1562284357887205497}}

== Status ==

Ships in cmpunlocker and is reproduced by everyone who runs it (shares the [[Driver unlock]] confirmation), so
{{Status|Proven}} as a software unlock. Reaching Gen2 '''x16''' additionally needs the capacitor mod.

== Related ==

[[Driver unlock]], [[PCIe Gen3 on the 10 GB card]], [[Cooling and power]], [[Platforms]],
[[Kernel parameters and module options]], [[Troubleshooting]].

{{ImportFooter}}
[[Category:Unlocks]]
[[Category:8 GB]]
[[Category:10 GB]]

Gen2 link retrain - Revision history